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Programmable High-g Digital Impact Sensor and Recorder ADIS16204
FEATURES
Dual-axis sensing, 70 g, 37 g 14-bit resolution Impact peak-level sample and hold RSS output Programmable event recorder 400 Hz double-pole Bessel sensor response Digitally controlled sensitivity and bias Digitally controlled sample rate, up to 4096 SPS Programmable condition monitoring alarms Auxiliary digital I/O Digitally activated self-test Embedded temperature sensor Programmable power management SPI-compatible serial interface Auxiliary 12-bit ADC input and DAC output Single-supply operation: +3.0 V to +3.6 V 4000 g powered shock survivability
FUNCTIONAL BLOCK DIAGRAM
AUX ADC AUX DAC VREF
ADIS16204
TEMPERATURE SENSOR INERTIAL MEMS SENSOR CS DIGITAL PROCESSING SPI PORT SCLK DIN SELF-TEST VDD DIGITAL CONTROL DOUT
SIGNAL CONDITIONING AND CONVERSION
POWER MANAGEMENT
ALARMS
AUXILIARY I/O
EVENT CAPTURE BUFFER MEMORY
06448-001
COM RST DIO1 DIO2
Figure 1.
APPLICATIONS
Crash or impact detection Condition monitoring of valuable goods Safety, shut-off sensing Impact event recording Security sensing, tamper detection
GENERAL DESCRIPTION
The ADIS16204 is a fully-contained programmable impact sensor in a single compact package enabled by the Analog Devices, Inc. iSensorTM integration. By enhancing the Analog Devices iMEMS(R) sensor technology with an embedded signal processing solution, the ADIS16204 provides tunable digital sensor data in a convenient format that can be accessed using a serial peripheral interface (SPI). The SPI provides access to measurements for dual-axis linear acceleration, a root sum square (RSS) of both axes, temperature, power supply, an auxiliary analog input, and an event capture buffer memory. Easy access to digital sensor data provides users with a system-ready device, reducing development time, cost, and program risk. Unique characteristics of the end system are accommodated easily through several built-in features, such as a single command in-system bias null/offset calibration, along with convenient sample rate control. The ADIS16204 offers the following embedded features, which eliminate the need for external circuitry and provide a simplified system interface: * * * * * * * Peak sample and hold Programmable event recording (dual, 1K x 16 bit) RSS output (total shock in the X-Y plane) Configurable alarms Auxiliary 12-bit ADC and DAC Configurable digital I/O port Digital self-test function
The ADIS16204 offers two power management features for managing system-level power dissipation: low power mode and a configurable shutdown feature. The ADIS16204 is available in a 9.2 mm x 9.2 mm x 3.9 mm laminate-based land grid array (LGA) package with a temperature range of -40C to +105C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved.
ADIS16204 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Recommended Pad Geometry.................................................... 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 10 Overview...................................................................................... 10 Acceleration Sensor.................................................................... 10 Temperature Sensor ................................................................... 10 Impact/Shock Response ............................................................ 10 Auxiliary ADC Function........................................................... 11 Basic Operation .............................................................................. 12 Serial Peripheral Interface......................................................... 12 Data Output Register Access .................................................... 13 Programming and Control............................................................ 14 Control Register Overview ....................................................... 14 Control Register Structure ........................................................ 14 Global Commands ..................................................................... 15 Calibration................................................................................... 15 Operational Control................................................................... 16 Status and Diagnostics............................................................... 17 Alarm Detection and Event Capture ....................................... 18 Second-Level Assembly ................................................................. 21 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22
REVISION HISTORY
6/07--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADIS16204 SPECIFICATIONS
TA = -40oC to +105C, VDD = 3.3 V, unless otherwise noted. Table 1.
Parameter ACCELEROMETER Output Full-Scale Range Sensitivity Nonlinearity Sensor-to-Sensor Alignment Error Cross-Axis Sensitivity Resonant Frequency OFFSET Zero-g Output 1 NOISE Noise Density FREQUENCY RESPONSE Sensor Bandwidth (-3 dB) Temperature Drift ACCELEROMETER SELF-TEST STATE 2 Output Change When Active Output Change When Active TEMPERATURE SENSOR Output at 25C Scale Factor ADC INPUT Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Gain Error Input Range Input Capacitance ON-CHIP VOLTAGE REFERENCE Accuracy Reference Temperature Coefficient Output Impedance DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity (DNL) Offset Error Gain Error Output Range Output Impedance Output Settling Time Conditions Axis X Y X Y Min 70 37 17.125 8.407 0.2 0.1 -5 24 X Y 10 Hz - 400 Hz, no postfiltering 2-pole Bessel |25C - TMIN| or |TMAX - 25C| At 25C X Y 360 0.2 0.2 1.8 400 2 254 518 1278 -2.13 12 2 1 4 2 0 During acquisition At 25C -10 40 70 5 k/100 pF to GND For Code 101 to Code 4095 12 4 1 5 0.5 0 to 2.5 2 10 Bits LSB LSB mV % V s 20 2.5 +10 2.5 440 +5 Typ Max Unit g g mg/LSB mg/LSB % Degrees % kHz g g mg/Hz Hz Hz LSB LSB LSB LSB/C Bits LSB LSB LSB LSB V pF V mV ppm/oC
Rev. 0 | Page 3 of 24
ADIS16204
Parameter LOGIC INPUTS 3 Input High Voltage, VINH Input Low Voltage, VINL Logic 1 Input Current, IINH Logic 0 Input Current, IINL Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL SLEEP TIMER Timeout Period 4 START-UP TIME Initial Reset recovery FLASH MEMORY Endurance 5 Data Retention 6 CONVERSION RATE Maximum Throughput Rate Minimum Throughput Rate POWER SUPPLY Operating Voltage Range, VDD Power Supply Current Conditions Axis Min 2.0 VIH = VDD VIL = 0 V 0.2 -40 10 2.4 0.4 0.5 130 2.5 20,000 20 4096 2.066 3.0 Normal mode, SMPL_TIME 0x08 (fs 910 Hz), at 25C Fast mode, SMPL_TIME 0x07 (fs 1024 Hz), at 25C Sleep mode, at 25C 3.3 12 37 150 3.6 15 43 128 0.8 1 -60 Typ Max Unit V V A A pF V V Seconds ms ms Cycles Years SPS SPS V mA mA A
ISOURCE = 1.6 mA ISINK = 1.6 mA
TJ = 85C
1 2 3 4 5 6
Note that gravity can impact this number, zero-g condition assumes both axes oriented normal to the earth's gravity.
Self-test response changes as the square of VDD.
Note that the inputs are +5 V tolerant.
Guaranteed by design. Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at -40C, +25C, +85C, and +105C.
Retention lifetime equivalent at junction temperature (TJ), 55C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature.
Rev. 0 | Page 4 of 24
ADIS16204
TIMING SPECIFICATIONS
TA = +25C, VCC = +3.3 V, unless otherwise noted. Table 2.
Parameter fSCLK tDATARATE tCSHIGH tCS tDAV tDSU tDHD tDF tDR tSFS
1 2
Description Fast mode2 Normal mode2 Chip select period, fast mode2 Chip select period, normal mode2 Chip select high Chip select to clock edge Data output valid after SCLK edge Data input setup time before SCLK rising edge Data input hold time after SCLK rising edge Data output fall time Data output rise time CS high after SCLK edge
Min1 0.01 0.01 40 100 1/fSCLK 48.8 24.4 48.8
Typ
Max1 2.5 1.0
Unit MHz MHz s s ns ns ns ns ns ns ns
100
5 5 5
12.5 12.5
Guaranteed by design; typical specifications are not tested or guaranteed. Based on sample rate selection.
tDATARATE
CS
06448-002
SCLK
Figure 2. SPI Chip Select Timing
CS
tCS
1 SCLK 2 3 4 5 6 15 16
tSFS
tDAV
DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB
tDSU
DIN W/R A5
tDHD
A4 A3 A2 D2 D1 LSB
06448-003
Figure 3. SPI Timing (Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)
Rev. 0 | Page 5 of 24
ADIS16204 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Acceleration (Any Axis, Unpowered, 0.5 ms) Acceleration (Any Axis, Powered, 0.5 ms) VCC to COM Digital Input/Output Voltage to COM Analog Inputs to COM Operating Temperature Range Storage Temperature Range Rating 4000 g 4000 g -0.3 V to +6.0 V -0.3 V to +5.5 V -0.3 V to +3.5 V -40C to +125C -65C to +150C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 6 of 24
ADIS16204 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VREF COM AUX ADC
14 16 15 Y 13 12
SCLK DOUT DIN CS
1 X
VDD
AUX DAC NC NC RST
06448-004
2
ADIS16204
TOP VIEW (Not to Scale)
11
3
10
4 5 6 7 8
9
NC
NOTES 1. PINS ARE NOT VISIBLE FROM THE TOP VIEW. THEY ARE SHOWN FOR CONVENIENCE IN CREATING CAD LIBRARY PARTS.
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5, 6 7, 8, 10, 11 9 12 13 14 15 16
1
Mnemonic SCLK DOUT DIN CS DIO1, DIO2 NC RST AUX DAC VDD AUX ADC VREF COM
Type 1 I O I I I/O - I O S I O S
Description SPI, Serial Clock. SPI, Data Out. SPI, Data In. SPI, Chip Select, Active Low. Multifunction Digital Input/Output Pins. No Connect. Reset, Active Low. This input resets the embedded microcontroller to a known state. Auxiliary DAC Analog Voltage Output. +3.3 V Power Supply. Auxiliary ADC Analog Input Voltage. Precision Reference Output. Common. Reference point for all circuitry.
S = supply; O = output; I = input.
RECOMMENDED PAD GEOMETRY
2.6955 8x 4.1865 8x
NC
NC = NO CONNECT
DIO1
DIO2
0.670 12x 8.373 2x 5.391 4x
1.127 16x 9.2mm x 9.2mm STACKED LGA PACKAGE
Figure 5. Example of a Pad Layout
Rev. 0 | Page 7 of 24
06448-005
0.500 16x
ADIS16204 TYPICAL PERFORMANCE CHARACTERISTICS
60% 0.5 0.4 50% 0.3
Y-AXIS BIAS OFFSET (g)
% OF POPULATION
40%
0.2 0.1 0 -0.1 -0.2
+1 SIGMA
30%
20%
-1 SIGMA
10% -0.3
06448-025
0.040
0.125
0.210
0.295
0
40 TEMPERATURE (C)
80
120
OFFSET BIAS (g)
Figure 6. Bias Offset Distribution, X-Axis
50% 45%
30 35
Figure 9. Offset Bias Change vs. Temperature, Y-Axis
40%
% OF POPULATION
30% 25% 20% 15% 10%
% OF POPULATION
35%
25 20 15 10 5
5% 0.045 0.040 0.125 OFFSET BIAS (g) 0.210 0.295
0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
0.18
06448-019 06448-020
0%
06448-026
0
TOTAL OFFSET BIAS CHANGE (g)
Figure 7. Bias Offset Distribution, Y-Axis
0.8
Figure 10. Offset Bias Change, X-Axis vs. Power Supply (3.0 V to 3.6 V)
25
0.6
20
X-AXIS BIAS OFFSET (g)
0.4 +1 SIGMA 0.2
% OF POPULATION
15
10
0
-1 SIGMA
-0.2
5
0
40 TEMPERATURE (C)
80
120
06448-015
-0.4 -40
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
TOTAL OFFSET BIAS CHANGE (g)
Figure 8. Offset Bias Change vs. Temperature, X-Axis
Figure 11. Offset Bias Change, Y-Axis vs. Power Supply (3.0 V to 3.6 V)
Rev. 0 | Page 8 of 24
06448-016
0%
-0.4 -40
ADIS16204
30
4.5
25
SELF-TEST RESPONSE (g)
4.3
% OF POPULATION
20
4.1
15
3.9
10
5
3.7
0.0170
0.0172
0.0174 0.0176 SENSITIVITY (g/LSB)
0.0178
0.0180
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 12. X-Axis Sensitivity Distribution
40 35
SUPPLY CURRENT (mA)
Figure 15. Self-Test Response (X and Y Axes) vs. Temperature
200
HIGH PERFORMANCE MODE
ACCELERATION MAGNITUDE (g) 150 ACTUAL ACCELERATION PROFILE 100 X_ACCL 50 Y_ACCL
30 25 20 15 10 5 0 2.8 NORMAL MODE
0
06448-023
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
0
20
40
60 SAMPLE
80
100
120
SUPPLY VOLTAGE (V)
Figure 13. Supply Current vs. Supply Voltage
400
Figure 16. Overrange Recovery, Sample Rate = 4096 SPS
300
SLEEP CURRENT (A)
200 +1 SIGMA
100
-1 SIGMA
-35
-20
-5
10
25
40
55
70
85
100
TEMPERATURE (C)
Figure 14. Sleep Current vs. Temperature
06448-032
0 -50
Rev. 0 | Page 9 of 24
06448-029
-50
06448-022
06448-027
0
3.5 -60
ADIS16204 THEORY OF OPERATION
OVERVIEW
The ADIS16204 integrates a dual-axis 70 g/37 g MEMS acceleration sensor into a complete impact/shock measurement and recording system. The integrated mixed signal processing circuit digitizes the sensor data, applies corrections factors, provides many user-programmable features, and offers a simple communication conduit: the serial peripheral interface (SPI).
IMPACT/SHOCK RESPONSE
The sensor's mechanical structure provides a linear measurement range that is 8 times that of each axis' actual output measurement range. Therefore, when considering the response to high-g, short duration events, the 2-pole, 400 Hz, low-pass Bessel filter network influences the output response. Figure 18 provides a frequency response for this signal chain. In Figure 19, the X-axis accelerometer experiences a 560 g shock event that lasts 0.1 ms, causing the output response to reach 70 g. For users that need to avoid output saturation, keeping the integration of the event's acceleration response (acceleration-time product in the case of Figure 19) below 56 g-ms is critical.
10 X: 418.9 Y: -3.291
ACCELERATION SENSOR
The ADIS16204 base sensor core provides a fully differential sensor structure and circuit path, resulting in substantial rejection of electromagnetic interference (EMI) effects. It uses electrical feedback with zero-force feedback for improved accuracy and stability. The sensor's resonant frequency is well beyond the cut-off frequency of the filter, which adds further noise rejection to the sensor signal conditioning circuit.
ANCHOR MOVABLE FRAME
0
MAGNITUDE (dB)
-10
-20
PLATE CAPACITORS
ACCELERATION
UNIT SENSING CELL
-30
FIXED PLATES
-40
UNIT FORCING CELL
MOVING PLATE
100 FREQUENCY (Hz)
1k
10k
Figure 18. ADIS16204 Frequency Response
ANCHOR
06448-006
600 550 500
IMPACT MAGNITUDE (g)
Figure 17. Simplified View of Sensor Under Acceleration
560g, 0.1ms, SIMULATED SHOCK
Figure 17 is a simplified view of one of the differential sensor elements. Each sensor includes several differential capacitor unit cells. Each cell is composed of fixed plates attached to the substrate and movable plates attached to the frame. Displacement of the frame changes the differential capacitance, which is measured by the on-chip circuitry. Complementary 200 kHz square waves drive the fixed plates. Electrical feedback adjusts the amplitudes of the square waves such that the ac signal on the moving plates is 0 V. The feedback signal is linearly proportional to the applied acceleration. This unique feedback technique ensures that there is no net electrostatic force applied to the sensor. The differential feedback control signal is also applied to the input of the filter, where it is filtered and converted to a single-ended signal.
450 400 350 300 250 200 150 100 50 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
06448-008
70g, FILTERED RESPONSE
0 -0.50 -0.25
TIME (ms)
Figure 19. ADIS16204 Shock Response
TEMPERATURE SENSOR
This sensor reflects the sensor's junction temperature and provides a convenient temperature measurement for systemlevel characterization and calibration feedback.
Rev. 0 | Page 10 of 24
06448-007
-50 10
ADIS16204
AUXILIARY ADC FUNCTION
The auxiliary ADC function integrates a standard 12-bit ADC into the ADIS16204 to digitize other system-level analog signals. The output of the ADC can be monitored through the AUX_ADC control register, as defined in Table 6. The ADC is a 12-bit successive approximation converter. The output data is presented in straight binary format with the full-scale range extending from 0 V to VREF. A high precision, low drift, factory calibrated 2.5 V reference is also provided. Figure 20 shows the equivalent circuit of the analog input structure of the ADC. The input capacitor (C1) is typically 4 pF and can be attributed to parasitic package capacitance. The two diodes provide ESD protection for the analog input. Care must be taken to ensure that the analog input signals never exceed the supply rails by more than 300 mV. This causes the diodes to become forward-biased and to start conducting. The diodes can handle 10 mA without causing irreversible damage. The resistor is a lumped component that represents the on resistance of the switches. The value of this resistance is typically 100 . Capacitor C2 represents the ADC sampling capacitor and is typically 16 pF.
C1 VDD D R1 C2
06448-010
D
Figure 20. Equivalent Analog Input Circuit Conversion Phase: Switch Open Track Phase: Switch Closed
For ac applications, removing high frequency components from the analog input signal is recommended by the use of a low-pass filter on the analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input must be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This can necessitate the use of an input buffer amplifier. When no input amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 k.
Rev. 0 | Page 11 of 24
ADIS16204 BASIC OPERATION
The ADIS16204 is designed for simple integration into industrial system designs, requiring only a power supply and a 4-wire, industry-standard SPI. The SPI provides access to the ADIS16204's register structure, which controls access to all sensor output data and controls for the device's programmable features. Each register is 16 bits in length and has its own unique bit map. The 16 bits in each register consist of an upper byte (Bit 8 to Bit 15) and a lower byte (Bit 0 to Bit 7), each of which has its own 6-bit address.
Writing to Registers
Figure 21 displays a typical data frame for writing a command to a control register. In this case, the first bit of the DIN sequence is a 1, followed by a 0, the 6-bit address, and the 8-bit data command. Because each write command covers a single byte of data, two data frames are required when writing to the entire 16-bit space of a register. The DIN bits clock into the ADIS16204 on the rising edge of SCLK.
SERIAL PERIPHERAL INTERFACE
The ADIS16204 SPI port includes four signals: chip select (CS), serial clock (SCLK), data input (DIN), and data output (DOUT). The CS line enables the ADIS16204 SPI port and frames each SPI event. When this signal is high, the DOUT lines are in a high impedance state and the signals on DIN and SCLK have no impact on operation. A complete data frame contains 16 clock cycles. Because the SPI port operates in full duplex mode, it supports simultaneous, 16-bit receive (DIN) and transmit (DOUT) functions during the same data frame. See Table 2, Figure 2, and Figure 3 for detailed timing and operation of the SPI port.
Reading from Registers
Reading the contents of a register requires a modification to the sequence in the DIN sequence Figure 21. As shown in Figure 22, the first two bits in the DIN sequence are 0, followed by six address bits. Each register has two addresses (upper, lower), but either one can be used to access its entire 16 bits of data. The final 8 bits of the DIN sequence are irrelevant and can be counted as don't cares during a read command. During the next data frame, the DOUT sequence contains the register's 16-bit data. The ADIS16204 clocks out the first DOUT bit on the falling edge of the CS line and clocks out the rest of the DOUT bits on the falling edges of the SCLK signal. Although a single read command requires two separate data frames, the full duplex mode minimizes this overhead, requiring only one extra data frame when continuously sampling.
CS
DATA FRAME
SCLK
DIN
W/R
A5
A4
A3
A2
A1
A0
DC7
DC6
DC5 DC4
DC3
DC2
DC1
DC0
WRITE = 1 READ = 0
REGISTER ADDRESS
DATA FOR WRITE COMMANDS DON'T CARE FOR READ COMMANDS
Figure 21. DIN Bit Sequence
CS
DATA FRAME
DATA FRAME
SCLK
DIN W/R BIT
ADDRESS ZERO
DON'T CARE
NEXT COMMAND
DOUT
BASED ON PREVIOUS COMMAND
16-BIT REGISTER CONTENTS
Figure 22. SPI Sequence for Read Commands
Rev. 0 | Page 12 of 24
06448-012
06448-011
ADIS16204
DATA OUTPUT REGISTER ACCESS
Table 6 provides an overview of each data output register, along with their function, address, and relevant decoding information. all output data registers in the ADIS16204. The upper byte is always first in register read sequences. Table 5. Output Bit Assignments
MSB ND D7 EA D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 LSB D8 D0
Sensor Output Data
The ADIS16204 provides access to X- and Y-axis acceleration measurements, combined accelerations measurements (root sum square of X and Y), peak acceleration, power supply measurements, temperature measurements, an auxiliary 12-bit ADC channel, and the event-capture buffer memory.
Peak Sample and Hold Output Registers
The ADIS16204 monitors the X, Y and XY acceleration measurements and holds the maximum value and polarity for each parameter. The X_PEAK_OUT, Y_PEAK_OUT, and XY_PEAK_OUT registers provide access to these maximum values. See the COMMAND register for clearing these registers.
The MSB holds the new data (ND) indicator. When the output registers are updated with new data, the ND bit goes to a 1 state. After the output data is read, it returns to a 0 state. The EA bit is used to indicate a system error or an alarm condition that can result from a number of conditions, such as a power supply that is out of the specified operating range (see the Status and Diagnostics section for more details). The output data is either 12 bits or 14 bits in length. For all of the 12-bit output data, Bit D13 and Bit D12 are assigned don't care status. The output data register map is located in Table 6 and provides all of the necessary details for accessing each register's data. Figure 23 provides an example of the SPI sequence.
Register Access
This output data is continuously updating internally, regardless of user read rates. The bit map in Table 5 describes the structure of Table 6. Data Output Register Information
Name SUPPLY_OUT XACCL_OUT YACCL_OUT AUX_ADC TEMP_OUT 1 X_PEAK_OUT 2 Y_PEAK_OUT2 XY_RSS_OUT 3 XY_PEAK_OUT2,3 CAPT_BUF_1 4 CAPT_BUF_24
1 2
Function Power supply X-axis acceleration Y-axis acceleration Auxiliary analog input data Sensor temperature data Peak, X-axis acceleration Peak, Y-axis acceleration X-Y combined acceleration (RSS) Peak, X-Y combined output (RSS) Capture Buffer 1 Output Register Capture Buffer 2 Output Register
Register 0x03, 0x02 0x05, 0x04 0x07, 0x06 0x09, 0x08 0x0B, 0x0A 0x0D, 0x0C 0x0F, 0x0E 0x19, 0x18 0x1B, 0x1A 0x1D, 0x1C 0x1F, 0x1E
Scale Factor Resolution (Bits) Data Format (per LSB) 12 Binary 1.22 mV 14 Twos complement 17.125 mg 14 Twos complement 8.407 mg 12 Binary 0.61 mV 12 Binary -0.47C 14 Twos complement 17.125 mg 14 Twos complement 8.407 mg 14 Binary 17.125 mg 14 Binary 17.125 mg See the Alarm Detection and Event Capture section, Table 37, and Table 38
25C, nominal output is equal to 1278 LSB. The peak levels in these registers accumulate, storing the greatest value measured (polarity is captured--except for XY_PEAK_OUT), until they are cleared using the COMMAND register. 3 This is a measure of the total shock absorbed by the package in the XY plane, and is the result of a root sum square of X and Y acceleration measurements. 4 See the Alarm Detection and Event Capture section for more details.
CS
SCLK
DIN
W/R BIT = 0
ADDRESS = 000101
DOUT DATA = 1011 1101 1101 1110 NEW DATA, NO ALARM, XACCL_OUT = -10.377g
06448-013
Figure 23. Example of an Output Timing/Coding Diagram
Rev. 0 | Page 13 of 24
ADIS16204 PROGRAMMING AND CONTROL
CONTROL REGISTER OVERVIEW
The ADIS16204 offers many programmable features controlled by writing commands to the appropriate control registers. The following features are available for configuration: * * * Global commands Calibration Operational control * Sample rate * Power management * DAC output * Digital I/O Operational status and diagnostics * Self-test * Status conditions * Alarms Event capture
CONTROL REGISTER STRUCTURE
The ADIS16204 uses a temporary, SRAM-based memory structure to facilitate the control registers displayed in Table 7. The start-up configuration is stored in a flash memory structure that automatically loads into the control registers during the start-up sequence. Each nonvolatile register has a corresponding flash memory location for storing the latest configuration contents. Because flash memory has endurance limitations, the contents of each nonvolatile register must be stored to flash manually. Note that the contents of the control register are only nonvolatile when they are stored to flash. The flash update command, made available in the COMMAND register, provides this function. The ENDURANCE register provides a counter, which allows for memory reliability management against the flash memory's write cycle specification.
*
*
Table 7. Control Register Mapping
Name ENDURANCE XACCL_NULL YACCL_NULL XACCL_SCALE YACCL_SCALE CAP_BUF_1 CAP_BUF_2 ALM_MAG1 ALM_MAG2 ALM_CTRL CAPT_PNTR AUX_DAC GPIO_CTRL MSC_CTRL SMPL_PRD CAPT_CFG SLP_CNT STATUS COMMAND
1 2
Type R R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W W R W
Volatility 1 Nonvolatile Nonvolatile Nonvolatile Nonvolatile Nonvolatile Volatile Volatile Nonvolatile Nonvolatile Nonvolatile Volatile Volatile Volatile Nonvolatile 2 Nonvolatile Nonvolatile Volatile Volatile N/A
Address 0x01, 0x00 0x02 to 0x0F 0x11, 0x10 0x13, 0x12 0x15, 0x14 0x17, 0x16 0x18 to to 0x1B 0x1D, 0x1C 0x1F, 0x1E 0x21, 0x20 0x23, 0x22 0x24 to 0x27 0x29, 0x28 0x2B, 0x2A 0x2A to 0x2F 0x31, 0x30 0x33, 0x32 0x35, 0x34 0x37, 0x36 0x39, 0x38 0x3B, 0x3A 0x3D, 0x3C 0x3F, 0x3E
Bytes 2 14 2 2 2 2 4 2 2 2 2 2 2 2 6 2 2 2 2 2 2 2 2
Function Flash memory write counter Output data registers X-axis offset null calibration register Y-axis offset null calibration register X-axis scale factor calibration register Y-axis scale factor calibration register Output data registers Capture buffer output register 1 Capture buffer output register 2 Alarm 1 amplitude threshold Alarm 2 amplitude threshold Reserved Alarm source control register Capture register address pointer Reserved Auxiliary DAC data Auxiliary digital I/O control register Miscellaneous control register ADC sample period control register Capture configuration register Counter used to determine length of power-down mode System status register System command register
Reference Table Table 26 Table 6 Table 10 Table 11 Table 12 Table 13 Table 6 Table 37, Table 38 Table 37, Table 38 Table 32, Table 34 Table 33, Table 34 Table 30, Table 31 Table 39, Table 40 Table 19, Table 20 Table 21, Table 22 Table 24, Table 25 Table 15, Table 16 Table 35, Table 36 Table 17, Table 18 Table 27, Table 28 Table 8, Table 9
In order to establish nonvolatile status, the flash memory must be updated after updating the control registers. Bit 8 clears after the internal self-test sequence completes, effectively making this bit volatile.
Rev. 0 | Page 14 of 24
ADIS16204
GLOBAL COMMANDS
The ADIS16204 provides global commands, which simplify many common operations. The COMMAND register provides command bits for each function. Writing a 1 to the assigned command bit exercises its function. The flash update copies the contents of all nonvolatile registers into their assigned, nonvolatile, flash memory locations. This process takes approximately 50 ms and requires a power supply that is within the specified operating range. After waiting the appropriate time for the flash update to complete, verify successful completion by reading the STATUS register (Flash update error = zero, if successful). If the flash update was not successful, reading this error bit will accomplish two things: (1) alert system processor to try again, and (2) clear the error flag, which is required for flash memory access. The software reset command restarts the internal processor, which loads all registers with the contents in their flash memory locations. The DAC data latch command loads the contents of AUX_DAC into the DAC latches. Because the AUX_DAC contents must be updated one byte at a time, this command ensures a stable DAC output voltage during updates. Table 9. COMMAND Bit Descriptions
Bit 15:11 10 9 8 7 6 5 4 3 2 1 0 Description Not used Reset capture pointer (set CAPT_PNTR to 0x0001) Clear capture flash (nonvolatile back-up) Clear capture buffer (SRAM) Software reset Copy capture buffer to nonvolatile flash Clear peak output registers, (reset them to 0x0000) Clear status register (reset all bits to 0) Flash update--saves nonvolatile register settings DAC data latch Factory calibration restore Autonull
CALIBRATION
In addition to the factory calibration, the ADIS16204 provides a user configurable calibration for systems that require accuracy improvements. For example, a vehicle system may require better resolution to separate a minor bump from a hard brake event. In cases like this, the ADIS16204 provides configuration registers that adjust both offset and sensitivity (gain) on both X- and Y-axes. The following relationship describes the calibration function: y = mx + b where: y is the calibrated output data. m is the scale factor multiplier [XACCL_SCALE/YACCL_SCALE]. x is the precalibration data. b is the offset adder [XACCL_NULL/YACCL_NULL]. Assuming zero offset and nominal scale factor (sensitivity), the offset adjustment range for the X-axis is 35.054 g and 17.527 g for the Y-axis. Assuming zero offset, the scale factor adjustment range is 0 to 2. Table 10. XACCL_NULL Register Definition
Address 0x11, 0x10
1
Calibration Commands
The autonull command provides a simple method for removing offset from the sensor outputs. This command takes separate 64-sample measurements for each axis (X, Y), then loads the opposite value into each axis' offset null register. The accuracy of this operation depends on zero force or motion during the 64-sample timeframe. The factory calibration restore sets the scale and offset null registers (XACCL_NULL, for example) back to their default values. For more information on ADIS16204 calibration, see the Calibration section.
Event Capture Commands
The COMMAND register provides four different functions that simplify the process of using the event capture function. The reset-capture pointer function sets the contents of the capture pointer to its initial value of 0x0001. The clear capture flash, clear capture buffer, and capture flash copy commands are selfdescriptive. The capture flash copy takes approximately 120 ms to complete and serves the purpose of copying the capture buffer into nonvolatile flash memory. See the Alarm Detection and Event Capture section for more information. Table 8. COMMAND Register Definition
Address 0x3F, 0x3E Default N/A Format N/A Access W only
Scale1 17.125 mg
Default 0x0000
Format Twos complement
Access R/W
Scale is the weight of each LSB.
Table 11. YACCL_NULL Register Definition
Address 0x13, 0x12
1
Scale1 8.407 mg
Default 0x0000
Format Twos complement
Access R/W
Scale is the weight of each LSB.
Table 12. XACCL_SCALE Register Definition
Address 0x15, 0x14
1 2
Scale1 0.0488%
Default2 0x0800
Format Binary
Access R/W
Scale is the weight of each LSB. Equates to a scale factor of one.
Rev. 0 | Page 15 of 24
ADIS16204
Table 13. YACCL_SCALE Register Definition
Address 0x17, 0x16
1 2
Scale 0.0488%
1
Default 0x0800
2
Format Binary
Access R/W
Scale is the weight of each LSB. Equates to a scale factor of one.
Table 14. Calibration Register Bit Descriptions
Bit 15:12 11:0 Description Not used Data bits
The sample rate setting also affects the power dissipation. When the sample rate is set below 1024 SPS, the power dissipation typically reduces by a factor of 68%. The two different modes of operation offer a system-level trade-off between performance (sample rate, serial transfer rate) and power dissipation.
Power Management
In addition to offering two different performance modes for power optimization, the ADIS16204 offers a programmable shutdown period. Writing the appropriate sleep time to the SLP_CNT register shuts the device down for the specified time. The following example provides an illustration of this relationship: B7 ... B0 = 00000110 Sleep period = 3 seconds After completing the sleep period, the ADIS16204 returns to normal operation. Table 17. SLP_CNT Register Definition
Address 0x3B, 0x3A
1
OPERATIONAL CONTROL
Internal Sample Rate
The internal sample rate defines how often data output variables are updated, independent of the rate at which they are read out on the SPI port. The SMPL_PRD register controls the ADIS16204 internal sample rate and has two parts: a selectable time base and a multiplier. The following relationship produces the sample rate: TS = TB x (NS + 1)
B
where: TS is the sample period. TB is the time base. NS is the increment setting.
B
Scale1 0.5 sec
Default 0x0000
Format Binary
Access W only
Scale is the weight of each LSB.
The default value is the maximum 4096 SPS, and the contents of this register are nonvolatile. Table 15. SMPL_PRD Register Definition
Address 0x37, 0x36 Default 0x0001 Format N/A Access R/W
Table 18. SLP_CNT Bit Descriptions
Bit 15:8 7:0 Description Not used Data bits
Auxiliary DAC
The auxiliary DAC provides a 12-bit level adjustment function. The AUX_DAC register controls the operation of this feature. It offers a rail-to-rail buffered output that has a range of 0 V to 2.5 V. The DAC can drive its output to within 5 mV of the ground reference when it is not sinking current. As the output approaches ground, the linearity begins to degrade (100 LSB beginning point). As the sink current increases, the nonlinear range increases. The DAC output latch function, contained in the COMMAND register, provides continuous operation while writing to each byte of this register. The contents of this register are volatile, which means that the desired output level must be set after every reset and power cycle event. Table 19. AUX_DAC Register Definition
Address 0x31, 0x30
1
Table 16. SMPL_PRD Bit Descriptions
Bit 15:8 7 6:0 Description Not used Time base 0 = 122.07 s, 1 = 3.784 ms Multiplier
Here is an example calculation of the sample period for the ADIS16204: If SMPL_PRD = 0x0007, B7 - B0 = 00000111 B7 = 0 TB = 122.07 s
B
B6...B0 = 000000111 NS = 7 TS = TB x (NS + 1) = 122.07 s x (7 + 1) = 976.56 s
B
fS = 1TS = 1024 SPS The sample rate setting has a direct impact on the SPI data rate capability. For sample rates of 1024 SPS and above, the SPI SCLK can run at a rate up to 2.5 MHz. For sample rates below 1024 SPS, the SPI SCLK can run at a rate up to 1 MHz.
Scale1 0.6105 mV
Default 0x0000
Format Binary
Access R/W
Scale is the weight of each LSB. In this case, it represents 4095 codes over the 2.5 V range out of output voltage.
Table 20. AUX_DAC Bit Descriptions
Bit 15:12 11:0 Description Not used Data bits
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ADIS16204
General-Purpose I/O
The ADIS16204 provides two general-purpose pins that enable digital I/O control using the SPI. The GPIO_CTRL control register establishes the configuration of these pins and handles the SPI-to-pin controls. Each pin provides the flexibility of both input (read) and output (write) operations. For example, writing a 0x0202 to this register establishes Line 1 as an input and Line 2 as an output that is in a 1 state. Writing 0x0000 to this register establishes both lines as inputs. When one (or both) of these lines is configured as an input, reading the assigned bit (Bit 8 and/or Bit 9) provides access to the input on this input pin. The digital I/O lines are also available for data-ready and alarm/ error indications. In the event of conflict, the following priority structure governs the digital I/O configuration: 1. 2. 3. GPIO_CTRL MSC_CTRL ALM_CTRL configure either of the general-purpose I/O pins (DIO1 and DIO2) as a data-ready indicator signal. When configured as a data ready indicator, the duty cycle is 20% (10% tolerance).
Self-Test
The MSC_CTRL register also provides a self-test function that verifies the mechanical integrity of the MEMS sensor. Selftest exercises the mechanical structure and signal conditioning circuit: from sensor element to data out. The internal test provides a simple, two-step process for checking the MEMS sensor: (1) start the process by writing a 1 to Bit 8 in the MSC_CTRL register, (2) wait 35 ms, and (3) check the result by reading Bit 5 of the STATUS register. The device is configured to perform a self-test at power on. Writing a 1 to Bit 10 of the MSC_CTRL register disables this function for future start-up sequences, reducing the start-up time. For reference, the result of the electrostatic deflection of each axis is available by reading the XACCL_OUT and/or YACCL_OUT registers. As an additional indicator of self-test, the new data bit is not active while in this mode. Table 24. MSC_CTRL Register Definition
Table 21. GPIO_CTRL Register Definition
Address 0x33, 0x32 Default 0x0000 Format N/A Access R/W
Address 0x35, 0x34
Default 0x0000
Format N/A
Access R/W
Table 22. GPIO_CTRL Bit Descriptions
Bit 15:10 9 8 7:2 1 0 Description Not used General-purpose I/O Line 2 polarity 1 = high, 0 = low General-purpose I/O Line 1 polarity 1 = high, 0 = low Not used General-purpose I/O Line 2, data direction control 1 = output, 0 = input General-purpose I/O Line 1, data direction control 1 = output, 0 = input
Table 25. MSC_CTRL Bit Descriptions
Bit 15:12 11 10 9 8 7:3 2 1 0 Description Not used Store capture to flash after capture buffer fills up 1 = enabled, 0 = disabled Self-test at power-on: 1 = disabled, 0 = enabled Not used Self-test enable (temporary, bit is volatile) 1 = enabled, 0 = disabled Not used Data-ready enable 1 = enabled, 0 = disabled Data-ready polarity 1 = active high, 0 = active low Data-ready line select: 1 = DIO2, 0 = DIO1
STATUS AND DIAGNOSTICS
The ADIS16204 provides a number of status and diagnostic functions. Table 23 provides a summary of these functions, along with their appropriate control registers. Table 23. Status and Diagnostic Functions
Function Data-ready I/O indicator Self-test, mechanical check for MEMS sensor Software check for error conditions Flash memory endurance Register MSC_CTRL MSC_CTRL STATUS ENDURANCE
Flash Memory Endurance
The ENDURANCE register maintains a running count of writes to the flash memory. This provides a convenient tool for managing the reliability of the on-chip memory. Once it reaches its maximum value of 32,767, it wraps around to zero and starts over. Table 26. ENDURANCE Register Definition
Address 0x01, 0x00 Default N/A Format Binary Access R only
Data-Ready I/O Indicator
The data-ready function provides an indication of new output data. The MSC_CTRL register provides the opportunity to
Rev. 0 | Page 17 of 24
ADIS16204
STATUS Conditions
The STATUS register contains the following error-condition flags: alarm conditions, self-test status, SPI communication failure, capture buffer full, control register update failure, and power supply out of range. See Table 27 and Table 28 for the appropriate register access and bit assignment for each flag. The bits assigned for checking power supply range automatically reset to zero when the error condition no longer exists. Clearing the remaining error-flag bits requires a single write command to the COMMAND register (write a 1 to Bit 4). See Table 8 and Table 9 for the configuration details of the COMMAND register. If the error condition still exists after exercising the COMMAND register to clear the bits, the appropriate error flag bit returns to 1 during the next sampling cycle. All bits in the STATUS register are volatile. Table 27. STATUS Register Definition
Address 0x3D, 0x3C Default 0x0000 Format N/A Access R only
and hardware options (DIO1 and DIO2 configuration, ALM_CTRL register). In addition, the programmable alarms can trigger an event capture function, which provides time recording, much like a single event capture function on a digital oscilloscope. Table 29 provides a summary of the functions available for configuring the alarms.
Alarm Configuration
Mark, I am just realizing this now, but I cannot bold normal text just for
1.
Program The Output Data To Monitor.
Essentially, this establishes the trigger source, by configuring the upper byte of the ALM_CTRL register. See Table 31 for the proper bit assignments. For example, the following pseudo code establishes X acceleration as the trigger for Alarm 2 and Y acceleration as the trigger for Alarm 1: * Write 0x23 to Address 0x29 [ALM_CTRL].
2.
Program The Trigger Levels And Polarity.
Table 28. STATUS Bit Descriptions
Bit 15:13 12 11:10 9 8 7:6 5 4 3 2 1 0 Description Not used Capture buffers full Not used Alarm 2 status 1 = active, 0 = inactive Alarm 1 status 1 = active, 0 = inactive Not used Self-test diagnostic error flag 1 = error condition, 0 = normal operation Not used SPI communications failure 1 = error condition, 0 = normal operation Flash update failed 1 = error condition, 0 = normal operation Power supply above 3.625 V 1 = above 3.625 V, 0 = below 2.975 V (normal) Power supply below 2.975 V 1 = below 2.975 V, 0 = above 2.975 V (normal)
This requires two write commands for each alarm, to the ALM_MAG1 and ALM_MAG2 registers. For example, use the following pseudo code to establish greater than 7.4 g as the trigger threshold for both channels: * * * * Write 0x81 to Address 0x21 [ALM_MAG1]. Write 0xB0 to Address 0x20 [ALM_MAG1]. Write 0x83 to Address 0x23 [ALM_MAG2]. Write 0x70 to Address 0x22 [ALM_MAG2].
The ALM_MAG1 and ALM_MAG2 values are calculated by: X = 7.4 g = 432 codes = 00 0001 1011 0000 (Bit 0 to Bit 13) Y = 7.4 g = 880 codes = 00 0011 0111 0000 (Bit 0 to Bit 13) Bit 15 in both registers must be set to 1 in order to denote greater than polarity.
3.
Set Up A Digital I/O Line As An Alarm Indicator.
This step requires configuration of the lower byte in the ALM_CTRL. If software monitoring, using the STATUS register, is the preferred alarm-checking method, then this step is not required. The following pseudo code establishes Digital I/O Line 2 as a positive signal, alarm indicator: * Write 0x07 to Address 0x28 [ALM_CTRL].
ALARM DETECTION AND EVENT CAPTURE
The ADIS16204 provides alarm detection and event capture functions, which monitor critical internal and external operating conditions. Six factory standard alarms monitor the AIDS16204 for normal operation. Two programmable alarms provide monitoring for system-critical conditions, which reduces external processing burden for this function. Alarm monitoring includes both software (STATUS register)
See Table 31 for the configuration options available for this function. As noted earlier, the digital I/O lines are shared, so use of them as an alarm indicator requires that it not be in use as a data-ready or general-purpose I/O pin.
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ADIS16204
Table 29. Alarm and Event Capture Configuration Registers
Register ALM_CTRL ALM_CTRL ALM_CTRL ALM_MAG1/ ALM_MAG 2 ALM_MAG1/ ALM_MAG 2 CAPT_CFG CAPT_CFG CAPT_CFG COMMAND COMMAND COMMAND COMMAND COMMAND MSC_CTRL SMPL_PRD Parameter/Function Alarm trigger source Capture buffer triggers Digital alarm output Alarm trigger levels Alarm trigger directions Capture data sources Capture buffer size Pretrigger data size Reset capture pointer Clear capture buffer Clear capture flash Clear buffer full flag Save captured data to nonvolatile flash Autosave captured data to nonvolatile flash Sample rate Default Setting None Disabled Disabled 0 Less than 1: X acceleration 2: Y acceleration 1024 samples 128 samples N/A N/A N/A N/A N/A Disabled 4096 SPS
Table 32. ALM_MAG1 Register Definition
Address 0x21, 0x20 Default 0x0000 Format N/A Access R/W
Table 33. ALM_MAG2 Register Definition
Address 0x23, 0x22 Default 0x0000 Format N/A Access R/W
Table 34. ALM_MAG1/ALM_MAG 2 Bit Designations
Bit 15 14 13:0 Description Comparison polarity 1 = greater than, 0 = less than Not used Data bits: format matches source data format (see Table 5 and Table 6)
Event Capture Overview
The ADIS16204 also provides a dual-channel, capture function. Figure 24 provides an example of a captured waveform. A dedicated set of programmable control registers govern the operation of this function, controlling the data source: trigger settings (level, direction and data source), memory depth, pretrigger data length, and data storage. In systems that require specific event monitoring, this feature simplifies system integration by reducing the burden on the system's processor. One convenient feature is the fact that the trigger source does not have to be the data that is captured.
20 DATA SOURCE: Y-AXIS ACCELERATION 15
Table 30. ALM_CTRL Register Definition
Address 0x29, 0x28 Default 0x0000 Format N/A Access R/W
Table 31. ALM_CTRL Bit Descriptions
Bit 15:12 Value 0000 0001 0010 0011 0100 0101 1000 11:8 7 6 5 4 3 2 1 0 Description Trigger source selection, Alarm 2 Disable Power supply X-acceleration Y-acceleration Auxiliary ADC Temperature sensor XY RSS acceleration Trigger source selection, Alarm 1 (See Alarm2) Not used Capture trigger activation, Alarm 2 1 = enabled, 0 = disabled Not used Capture trigger activation, Alarm 1 1 = enabled, 0 = disabled Not used Alarm indicator, using DIO1/2 1 = enabled, 0 = disabled Alarm indicator polarity 1 = active high, 0 = active low Alarm indicator line selection 1 = DIO2, 0 = DIO1
Y-AXIS IMPACT MAGNITUDE (g)
10 TRIGGER THRESHOLD: 7.4g 5 0 -5 -10 -15 -20
PRE-TRIGGER DATA LENGTH
06448-014
0
100
200
300
400
500
600
700
800
900
1000
SAMPLE - fs = 4096SPS
Figure 24. Event Capture Example
Event Capture Configuration
The event capture buffers use the alarms as their trigger source. Therefore, the first two configuration steps are the same. After setting the trigger data source(s) and threshold(s), follow these steps to complete the event capture setup:
1.
Program The Data Source To Capture.
This requires a single write cycle, to configure the upper byte of the CAPT_CFG register. For example, use the following pseudo code to set X acceleration and Y acceleration as the data sources for Capture Buffer 2 and Capture Buffer 1 respectively: * Write 0x23 to Address 0x39 [CAPT_CFG].
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ADIS16204
2. Configure the Capture Back-up Memory. Event Capture Data Access
Two output registers provide the necessary access for the ADIS16204's capture buffers: CAPT_BUF_1 and CAPT_BUF_2. At the completion of a capture event, the contents of theses registers contain the first sample from each buffer. Figure 25 provides a diagram that displays the role played by the CAPT_PNTR register in this process. This register provides a pointer function and automatically increments every time one of the CAP_BUF_x registers are read. If efficient data transfer rates are a primary goal, then read all of the contents of one buffer, before moving to the other buffer. Because the CAPT_PNTR offers both read and write access, individual buffer locations can be accessed by writing the sample number into this register.
CAPT_BUF_1 BUFFER 1 CAPT_BUF_2 BUFFER 2
Setting Bit 11 of the MSC_CTRL register to a 1 enables the event capture back-up function, effectively making it nonvolatile. When enabled, this function copies the contents of the capture buffer (right after it fills) to flash memory and restores it upon reset or powering the device on. It continues to do so until the buffer is cleared, using the COMMAND register. To enable this feature, use the following pseudo code: * Write 0x08 to Address 0x35 [MSC_CTRL].
3.
Clear The Capture Memory Locations.
Use the following pseudo code to clear both the normal capture locations (SRAM) and their respective flash memory locations: * Write 0x03 to Address 0x3F [COMMAND].
4. 5.
Set Up A Digital I/O Line As An Alarm Indicator. Set Each Alarm As A Trigger Source For The Buffer.
These steps require configuration of the lower byte in the ALM_CTRL register. The following pseudo code establishes Digital I/O Line 2 as a positive signal, alarm indicator, if necessary. It also arms both triggers for the event recorder. * Write 0x57 to Address 0x28 [ALM_CTRL].
USER ACCESIBLE INTERNAL MEMORY STRUCUTRE
06448-030
If a digital alarm indicator function were not required, the pseudo code would be: * Write 0x50 to Address 0x28 [ALM_CTRL].
CAPT_PNTR
Figure 25. Event Capture Buffer Memory Structure
Table 35. CAPT_CFG Register Definition
Address 0x39, 0x38 Scale N/A Default 0x327A Format N/A Access R/W
Table 37. Capture Register Definitions
Address CAPT_BUF_1 CAPT_BUF_2 Address 0x1D, 0x1C 0x1E, 0x1F Format The format and scale match that of the output data being monitored Access R only
Table 36. CAPT_CFG Bit Descriptions
Bit 15:12 Description Data source for Capture Buffer 2 0001= power supply 0010= X-axis acceleration 0011= Y-axis acceleration 0100= auxiliary ADC 0101= temperature sensor 1000= XY RSS acceleration Data source for Capture Buffer 1 (See Capture Buffer 2 for binary coding) Pretrigger Length: Power of two setting determines length. 0111b = 7d, which corresponds to 27 = 128 samples. If this setting is greater than the data length, its value is truncated and all captured samples are prior to the trigger Capture buffer length: Power of two setting determine length. 1010b = 10d, which corresponds to 210 = 1024 samples. The lowest setting is a 3, which corresponds to 8 samples
Table 38. CAPT_BUF_1 and CAPT_BUF_2 Bit Descriptions
Bit 15 14 13:0 Description Not used Error/alarm condition (use to identify transition between pre-trigger and post-trigger data) Data bits. Format matches that of the data source
11:8 7:4
Table 39. CAPT_PNTR Register Definition
Address 0x2B, 0x2A Scale N/A Default N/A Format Binary Access R/W
Table 40. CAPT_PNTR Bit Descriptions
Bit 15:11 10:0 Description Not used Capture address pointer: A binary number from 1 to 1024, which identifies the address of each individual capture buffer sample.
3:0
Rev. 0 | Page 20 of 24
ADIS16204 SECOND-LEVEL ASSEMBLY
The ADIS16204 can be attached to the second-level assembly board using SN63 (or equivalent) or a Pb-free solder. Figure 26 and Table 41 provide acceptable solder reflow profiles for each solder type. Note that these profiles may not be the optimum profile for the user's application. In no case should 260C be exceeded. It is recommended that the user develop a reflow profile based upon the specific application. In general, keep in mind that the lowest peak temperature and shortest dwell time above the melt temperature of the solder results in less shock and stress to the product. In addition, evaluating the cooling rate and peak temperature can result in a more reliable assembly.
TP RAMP-UP CRITICAL ZONE TL TO TP
tP
TEMPERATURE
TL
TSMAX TSMIN
tL
tS
PREHEAT
RAMP-DOWN
06448-031
t25C TO PEAK TIME
Figure 26. Acceptable Solder Reflow Profiles
Table 41. Acceptable Solder Reflow Profiles 1
Profile Feature Average Ramp Rate (TL to TP) Preheat Minimum Temperature (TSMIN) Maximum Temperature (TSMAX) Time (TSMIN to TSMAX) (ts) TSMAX to TL Ramp-Up Rate Time Maintained Above Liquidous Temperature(TL) Liquidous Temperature (TL) Time (tL) Peak Temperature (TP) Time Within 5C of Actual Tp Ramp-Down Rate Time 25C to TP
1
Sn63/Pb37 3C/sec max 100C 150C 60 sec to 120 sec 3C/sec 183C 60 sec to 150 sec 240C + 0C/-5C 10 sec to 30 sec 6C/sec max 6 min max
Condition Pb-Free 3C/sec max 150C 200C 60 sec to180 sec 3C/sec 217C 60 sec to 150 sec 260C + 0C/-5C 20 sec to 40 sec 6C/sec max 8 min max
Per IPC/JEDEC J-STD-020C.
Rev. 0 | Page 21 of 24
ADIS16204 OUTLINE DIMENSIONS
9.35 MAX 2.6955 BSC (8x) 5.391 BSC (4x) PIN 1 INDICATOR 1.000 BSC (16x)
1
13 12
16
9.20 TYP
8.373 BSC (2x) 0.797 BSC (12x)
9 8 5 4
TOP VIEW
5.00 TYP
0.200 MIN (ALL SIDES)
BOTTOM VIEW
0.373 BSC (16x)
3.90 MAX
022007-B
SIDE VIEW
Figure 27. 20-Terminal Land Grid Array [LGA] (CC-16-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADIS16204BCCZ 1 ADIS16204/PCBZ1
1
Temperature Range -40C to +105C
Package Description 16-Terminal Land Grid Array [LGA] Evaluation Board
Package Option CC-16-2
Z = RoHS Compliant Part.
Rev. 0 | Page 22 of 24
ADIS16204 NOTES
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ADIS16204 NOTES
(c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06448-0-6/07(0)
Rev. 0 | Page 24 of 24

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